NTC (Negative Temperature Coefficient) thermistors are used in many electrical and electronic products including mobile phones, PCs and their peripherals, secondary batteries, LCDs, etc. for measurement, adjustment, compensation and time delay of their temperature, and voltage adjustment and noise reduction.
For most temperature sensing applications the NTC thermistors are made of spinel manganite.
Thick film thermistors are of several types such as sandwich, multilayer, segmented and interdigitated, and the methods of calculating resistivity and B value for these types are different.
Multilayer NTC thermistors are made up of inner metal electrodes and paralleled layers of NTC thermistor ceramics. In the process of manufacturing, stresses are produced between the components of multilayer NTC thermistors due to mechanical, thermal and electrical loads.
These stresses in multilayer electronic components can be simulated through the finite element method (FEM) and calculated by analytical models and measured by X-ray diffraction (XRD).
Compared to other methods, FEM proves to be more convenient for analysis of more detailed overall stresses in multilayer electronic components under various loads.
Up to now, scientists have often used two-dimensional models for considering the details of multilayer thermistors, but these models cannot fully display the distribution of stresses of multilayer thermistors.
Therefore, 3D finite element analyses (FEA) are more suitable for further study into the effects of the design parameters of multilayer thermistors on the stresses.
The research results show that manipulation of the length of the lateral margin most significantly influences the maximum principal stress experienced in multilayer thermistors during soldering process. In addition, the number of inner electrodes also contributes to the tensile stress that occurs in the soldering process.
More information about this can be found in the paper “The Simulation Study on Internal Stress in Multilayer Thermistors during Soldering Process” presented by Yu Nam Chol, a researcher at the Science Engineering Institute, to the SCI Journal “Solid State Electronics Letters”.
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